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Reconfigurable Computing and FPGAs, International Conference on (2009)
Cancun, Quintana Roo, Mexico
Dec. 9, 2009 to Dec. 11, 2009
ISBN: 978-0-7695-3917-1
pp: 24-29
Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This paper describes fully-fledged implementations of single-precision floating point units for a MIPS processor architecture implementation. These coprocessors take as little room as 6% of a medium-sized FPGA, while the processor CPU may take only 2% of the same device. The space exploration process described here values the area and performance metrics and considers variations on the choice of synthesis tool, floating point unit generation method and architectural issues like clocking schemes. The conducted experiments show reductions of up to 22 times in clock cycles count for typical floating point application modules, compared to the use of software-emulated floating point processing.
floating point hardware, FPGA, embedded processor, GALS design, prototyping
Ney L. V. Calazans, Fernando G. Moraes, Taciano A. Rodolfo, "Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area", Reconfigurable Computing and FPGAs, International Conference on, vol. 00, no. , pp. 24-29, 2009, doi:10.1109/ReConFig.2009.26
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