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Reconfigurable Computing and FPGAs, International Conference on (2005)
Puebla City, Mexico
Sept. 28, 2005 to Sept. 30, 2005
ISBN: 0-7695-2456-7
TABLE OF CONTENTS
Introduction

Preface (PDF)

pp. viii
Cover
Introduction
Session 1: Image Processing

Real-Time FPGA-Based Architecture for Bicubic Interpolation: An Application for Digital Image Scaling (Abstract)

Miguel O. Arias-Estrada , National Institute for Astrophysics, Optics and Electronics
Marco Aurelio Nuño-Maganda , National Institute for Astrophysics, Optics and Electronics
pp. 1

An Image Comparison Circuit Design (Abstract)

Adriano De Luca Pennacchia , Centro de Investigación y Estudios Avanzados del IPN
Miguel Angel Sánchez Martínez , Centro de Investigación y Estudios Avanzados del IPN
pp. 2

FPGA-Based Customizable Systolic Architecture for Image Processing Applications (Abstract)

Griselda Saldaña , National Institute for Astrophysics, Optics and Electronics
Miguel Arias-Estrada , National Institute for Astrophysics, Optics and Electronics
pp. 3
Session 2: Arithmetic
Session 3: Architecture

Rapid Prototyping of a Self-Timed ALU with FPGAs (Abstract)

S. Ortega-Cisneros , Universidad Autónoma de Madrid
E. Boemo , Universidad Autónoma de Madrid
J. J. Raygoza-Panduro , Universidad Autónoma de Madrid
J. Suardíaz Muro , Universidad de Cartagena
pp. 7

FPGA Implementation of a Synchronous and Self-Timed Neuroprocessor (Abstract)

S. Ortega-Cisneros , Universidad Autónoma de Madrid
E. Boemo , Universidad Autónoma de Madrid
J. J. Raygoza-Panduro , Universidad Autónoma de Madrid
pp. 8
Session 4: Reconfiguration

On the Design of Two-Level Reconfigurable Architectures (Abstract)

Martin Middendorf , University of Leipzig
Sebastian Lange , University of Leipzig
pp. 9

A Secure Self-Reconfiguring Architecture Based on Open-Source Hardware (Abstract)

Pablo Huerta , Universidad Rey Juan Carlos
Javier Castillo , Universidad Rey Juan Carlos
Victor López , Universidad Rey Juan Carlos
José Ignacio Martínez , Universidad Rey Juan Carlos
pp. 10
Session 5: Tools

VANNGen: A Flexible CAD Tool for Hardware Implementation of Artificial Neural Networks (Abstract)

Maurício Ayala-Rincón , Universidade de Brasília
Ricardo P. Jacobi , Universidade de Brasília
Carlos H. Llanos , Universidade de Brasília
André L. S. Braga , Universidade de Brasília
pp. 13
Session 6: Physical Design

Design Space Exploration of Coarse-Grain Reconfigurable DSPs (Abstract)

Rainer G. Spallek , Dresden University of Technology
Martin Zabel , Dresden University of Technology
Steffen Köhler , Dresden University of Technology
Martin Zimmerling , Dresden University of Technology
Thomas B. Preußer , Dresden University of Technology
pp. 15

Optimizing Register Binding in FPGAs Using Simulated Annealing (Abstract)

Iyad Ouaiss , Lebanese American University
Annie Avakian , Lebanese American University
pp. 16
Session 7: Architecture 2

An FPGA Parallel Sorting Architecture for the Burrows Wheeler Transform (Abstract)

René Cumplido , National Institute of Astrophysics, Optics and Electronics
José Martínez , National Institute of Astrophysics, Optics and Electronics
Claudia Feregrino , National Institute of Astrophysics, Optics and Electronics
pp. 17
Session 8: Tools 2

Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic Devices (Abstract)

Corey J. Milliord , University of Central Florida
C. A. Sharma , University of Central Florida
R. F. DeMara , University of Central Florida
pp. 18

Applied VHDL Training Methodology, EDA Framework and Hardware Implementation Platform (Abstract)

Martin O? Halloran , National University of Ireland - Galway
Patrick Rocke , National University of Ireland - Galway
Fearghal Morgan , National University of Ireland - Galway
pp. 19
Short Papers

FPGA Implementation of DSVPWM Modulator (Abstract)

Hannu Sarén , Lappeenranta University of Technology
Kimmo Rauma , Lappeenranta University of Technology
Ossi Laakkonen , Lappeenranta University of Technology
Olli Pyrhönen , Lappeenranta University of Technology
pp. 20

A Novel FPGA Implementation of a Welding Control Using a New Bus Architecture (Abstract)

T. Härkönen , Lappeenranta University of Technology
O. Pyrhönen , Lappeenranta University of Technology
I. Pajari , Lappeenranta University of Technology
K. Rauma , Lappeenranta University of Technology
J. Luukko , Lappeenranta University of Technology
pp. 21

VHDL Core for 1024-Point Radix-4 FFT Computation (Abstract)

Alejandro Ordaz-Moreno , Universidad de Guanajuato
Rene de Jesus Romero-Troncoso , Universidad de Guanajuato
Jose Alberto Vite-Frias , Universidad de Guanajuato
pp. 24

FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m) (Abstract)

Mario Alberto García-Martínez , Instituto Tecnológico de Orizaba
Rubén Posada-Gómez , Instituto Tecnológico de Orizaba
Guillermo Morales-Luna , CINVESTAV, IPN
pp. 26

Hardware/Software Implementation of a Discrete Cosine Transform Algorithm Using SystemC (Abstract)

A. Avila , ITESM Campus Monterrey
S. O. Martinez , ITESM Campus Monterrey
R. Santoyo , ITESM Campus Monterrey
G. Dieck , ITESM Campus Monterrey
pp. 28
Author Index

Author Index (PDF)

pp. 29
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