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Pacific Rim International Symposium on Fault-Tolerant Systems (1997)
Taipei, TAIWAN
Dec. 15, 1997 to Dec. 16, 1997
ISBN: 0-8186-8212-4
TABLE OF CONTENTS
Session A1: Fault Tolerant Architectures

A Fault-Tolerant Embedded Microcontroller Testbed (Abstract)

Malena Mesarina , University of California at Los Angeles
Douglas W. Caldwell , University of California at Los Angeles
Riki Hwang , University of California at Los Angeles
David A. Rennels , University of California at Los Angeles
pp. 7

A Cache Error Propagation Model (Abstract)

A.K. Somani , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
K.S. Trivedi , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 15

An Embedded Fail-Safe Interlocking System (Abstract)

Yinghua Min , Institute of Computing Technology, Academia Sinica, Beijing
Bin Pei , China Railway Signal and Communication Co.
pp. 22

Phaeton: A Log-based Architecture for High Performance File Server Design (Abstract)

Charles Changli Chin , National Cheng Kung University
Shang-Rong Tsai , National Cheng Kung University
Chung-Kie Tung , National Cheng Kung University
pp. 28
Session B1: Error Detection and Correction

Double and Triple Error Detecting Capability of Internet Checksum and Estimation of Probability of Undetectable Error (Abstract)

Yoshihisa Desaki , Tokyo Metropolitan University
Daisuke Yokota , Tokyo Metropolitan University
Kazuhiko Iwasaki , Tokyo Metropolitan University
Yukiya Miura , Tokyo Metropolitan University
pp. 47

A System Solution to Reducing Frequency of Memory Repairs (Abstract)

M. Hsiao , IBM Corporation, Poughkeepsie, NY
C. Chen , IBM Corporation, Poughkeepsie, NY
pp. 53

Concurrent Error Detection In Priority Queue Managers For ATM Networks (Abstract)

Yoon-Hwa Choi , Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea
pp. 59
Session A2: Modeling and Tools

Adaptive System-Level Diagnosis and Its Application (Abstract)

Sying-Jyan Wang , National Chung-Hsing University
pp. 66

Fault Coverage Estimation Model For Partially Testable Multichip Modules (Abstract)

Wang-Dauh Tseng , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Kuochen Wang , Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 72

Reliability Modeling of Structured Systems: Exploring Symmetry in State-Space Generation (Abstract)

Arun K. Somani , Department of Electrical and Computer Engineering Iowa State University
pp. 78

Engineering Oriented Dependability Evaluation: MEADEP and Its Applications (Abstract)

Jeffrey Agron , SoHaR Incorporated, Beverly Hills, California, USA
Dong Tang , SoHaR Incorporated, Beverly Hills, California, USA
Myron Hecht , SoHaR Incorporated, Beverly Hills, California, USA
Herbert Hecht , SoHaR Incorporated, Beverly Hills, California, USA
Jeffrey Miller , SoHaR Incorporated, Beverly Hills, California, USA
pp. 85

Hierarchical Modeling And Dependability Evaluation Of Distributed Systems (Abstract)

T. Tsuchiya , Dept. of Inf. & Math. Sci., Osaka Univ., Japan
T. Kikuno , Dept. of Inf. & Math. Sci., Osaka Univ., Japan
Eun Hye Choi , Dept. of Inf. & Math. Sci., Osaka Univ., Japan
pp. 91
Session B2: Replica Control and Protocols

An Extended Binary Tree Quorum Strategy for K-Mutual Exclusion in Distributed Systems (Abstract)

Ye-In Chang , National Sun Yat-Sen University
Bor-Hsu Chen , National Sun Yat-Sen University
pp. 110

A New Quorum-Based Replica Control Protocol (Abstract)

Yao-Jen Chang , National Chiao-Tung University
Her-Kung Chang , Chang Gung College of Medicine and Technology
Shyan-Ming Yuan , National Chiao-Tung University
Yu-Ting Wu , National Chiao-Tung University
pp. 116
Session A3: Fault Tolerant Systems

The Adaptable Distributed Recovery Block Scheme And A Modular Implementation Model (Abstract)

J. Goldberg , California Univ., Irvine, CA, USA
C. Subbaraman , California Univ., Irvine, CA, USA
T.F. Lawrence , California Univ., Irvine, CA, USA
K.H. Kim , California Univ., Irvine, CA, USA
pp. 131

Checkpointing Message-Passing Interface(MPI) Parallel Programs (Abstract)

Jyh-Jong Tsay , National Chung Cheng University
Wei-Jih Li , National Chung Cheng University
pp. 147

Fault Handling Mechanisms in The RETHER Protocol (Abstract)

Chitra Venkatramani , State University of New York at Stony Brook
Tzi-cker Chiueh , State University of New York at Stony Brook
pp. 153
Session B3: System Evaluation

Design of A Fault-Tolerant Microprocessor: A Simulation Approach (Abstract)

Gwan Choi , Texas A&M University
Kab Joo Lee , Samsung Electronics Inc.
pp. 161

Reliability Simulation of Fault-Tolerant Software and Systems (Abstract)

Kishor S. Trivedi , Duke University
Swapna S. Gokhale , Duke University
Michael R. Lyu , Lucent Technologies, Bell Laboratories
pp. 167

Behavior of a Computer Based Interlocking System under Transient Hardware Faults (Abstract)

L. Romano , University of Illinois
N. Mazzocca , Universita' degli Studi di Napoli
R. K. Iyer , University of Illinois
A. Mazzeo , Universita' degli Studi di Napoli
Z. Kalbarczyk , University of Illinois
pp. 174

Performance Analysis Of A Reliable Real-Time Token-Ring Protocol (Abstract)

J.K. Muppala , Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
Jiannong Cao , Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
pp. 180
Session A4: Checkpointing and Transaction Processing

Checkpointing in CosMiC: A User-Level Process Migration Environment (Abstract)

Kiem-Phong Vo , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
Y. Huang , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
S. Yajnik , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
Yi-Min Wang , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
P.E. Chung , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
G. Fowler , Bell Labs., Lucent Technol., Murray Hill, NJ, USA
pp. 187

Time-Lag Duplexing - A Fault Tolerance Technique for Online Transaction Processing Systems (Abstract)

D. C. Bossen , International Business Machines Corporation
Arun Chandra , International Business Machines Corporation
pp. 202

Increasing Software Reliability through Rollback and On-line Fault Repair (Abstract)

Pankaj Jalote , Indian Institute of Technology
Deepak Gupta , Indian Institute of Technology
pp. 208
Session B4: Neural Networks and Formal Verification

Fault Tolerant Constructive Algorithm For Feedforward Neural Networks (Abstract)

K. Kaneko , Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
T. Ohmameuda , Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
N.C. Hammadi , Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
H. Ito , Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
pp. 215

The Use of Neurons with Higher Functionality to Enhance the Fault Tolerance of Neural Networks (Abstract)

Takuya Iwata , System LSI Laboratory, Fujitsu Laboratories.
Yoshihiro Tohma , Tokyo Denki University
pp. 221

An Implementation Of The FTAG Model In Concurrent ML (Abstract)

T. Katayama , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
M. Suzuki , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
R.D. Schlichting , Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
pp. 229

Formal Verification of a TDMA Protocol Start-Up Mechanism (Abstract)

Henrik Lönn , Chalmers University of Technology
Paul Pettersson , Uppsala University
pp. 235

Index of Authors (PDF)

pp. 243
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