16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) (2014)
Torino, Italy Italy
Feb. 12, 2014 to Feb. 14, 2014
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PDP.2014.107
Sunil Kumar , Scuola Superiore SantAnna, Pisa, Italy
Giuseppe Lipari , Scuola Superiore SantAnna, Pisa, Italy
The next generation of processor will contain an increasing number of cores, connected to the main memory and to each other using fast Network-on-Chip (NoC) organised in complex mesh structures. In order to analyse real-time programs running on such architectures, it is necessary to estimate the communication latency between processes running on different cores. The goal of this paper is to propose an analytic model for bounding the communication latency on NoC for many-core architectures. In particular, we introduce a new approach to analyse the communication latency on NoC with wormhole switching and credit-based virtual channel flow control. The proposed model is evaluated by comparing the results predicted by the model with real measurements obtained running a set of experiments on an Intel SCC platform.
Program processors, Mathematical model, Tiles, Switches, Equations, Computer architecture, System-on-chip
S. Kumar and G. Lipari, "Latency Analysis of Network-on-Chip Based Many-Core Processors," 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)(PDP), Torino, Italy Italy, 2014, pp. 432-439.