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16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) (2008)
Feb. 13, 2008 to Feb. 15, 2008
ISSN: 1066-6192
ISBN: 978-0-7695-3089-5
pp: 12-19
ABSTRACT
Microprocessor architecture for both commercial and academical purposeis coming into a new generation: multiprocessors on a chip. Togetherwith this novel architecture, questions and research topics alsoarise. For example, how to design the on-chip caches to avoid memoryoperations becoming the performance bottleneck?In this work, we study the impact of various cache architectures onthe execution behavior of multi-threading applications. We focus onfour general design issues: cache structure, configuration parameters,coherence influence, and prefetching strategies. The study is based on aself-developed cache simulator that models the functionality ofa multicore cache hierarchy with arbitrary levels and variousorganizations. The achieved results can direct both hardware and programdevelopers to optimize their cache designs or the program codes.
INDEX TERMS
Cache performance, Multicore processor, Simulation, OpenMp application
CITATION

J. Tao, M. Kunze and W. Karl, "Evaluating the Cache Architecture of Multicore Processors," 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)(PDP), vol. 00, no. , pp. 12-19, 2008.
doi:10.1109/PDP.2008.22
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