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16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) (2007)
Naples, Italy
Feb. 7, 2007 to Feb. 9, 2007
ISSN: 1066-6192
ISBN: 0-7695-2784-1
pp: 238-245
Guoping Long , Institute of Computing Technology, Chinese Academy of Sciences
Xuehai Qian , Institute of Computing Technology, Chinese Academy of Sciences
Junchao Zhang , Institute of Computing Technology, Chinese Academy of Sciences
Dongrui Fan , Institute of Computing Technology, Chinese Academy of Sciences
He Huang , Institute of Computing Technology, Chinese Academy of Sciences
Hao Zhang , Institute of Computing Technology, Chinese Academy of Sciences
ABSTRACT
This paper presents a framework for implementing the X86 FP stack used in an x86-compliant processor based on a general RISC architecture. Architectural supports are added to a typical RISC architecture to maintain the FP stack status. Some speculative techniques are applied to the decode stage to enable pipelined and efficient FP operations. An optimized register renaming scheme is proposed to eliminate redundant micro-ops in FP programs, resulting in an increased performance while mitigating the burden on register rename table. The simulation results show that on average more than 10% fmov micro-ops are removed. Elimination of micro-ops significantly speeds up the execution of programs. The IPC increases are as high as 30% for some programs, and near 10% on average.
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CITATION
Guoping Long, Xuehai Qian, Junchao Zhang, Dongrui Fan, He Huang, Hao Zhang, "Design and Implementation of Floating Point Stack on General RISC Architecture", 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), vol. 00, no. , pp. 238-245, 2007, doi:10.1109/PDP.2007.34
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