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16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) (2003)
Genova, Italy
Feb. 5, 2003 to Feb. 7, 2003
ISSN: 1066-6192
ISBN: 0-7695-1875-3
pp: 31
Jie Tao , Technische Universit?t M?nchen
ABSTRACT
Memory system is one of the most important issues which exhibit a critical impact on the performance of applications running on both uni-and multi-processors. This paper presents a simulation approach capable of collecting detailed information about the complete memory hierarchy, providing thereby feedback that can support explicit optimizations as well as automatic tuning of programs with respect to memory efficiency. The deployed simulator is a flexible and independent component modeling an existed hardware monitor which observes the inter-node communications. The monitor simulator is also capable of tracing the transactions within a single rocessor. In addition, it can be optionally combined with any level of the entire memory system and used in combination with various simulation tool. This allows a collection of accurate and comprehensive performance data, while keeping the monitoring component extensible, portable, and well applicable.
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CITATION

J. Tao, "Supporting the Memory System Evaluation with a Monitor Simulator," 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)(PDP), Genova, Italy, 2003, pp. 31.
doi:10.1109/EMPDP.2003.1183562
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