Acceleration of Image Processing Algorithms Using Minimal Resources of Custom Reconfigurable Hardware
2012 16th Panhellenic Conference on Informatics (2012)
Piraeus, Greece Greece
Oct. 5, 2012 to Oct. 7, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCi.2012.11
The hardware/software implementation of a custom vision board using minimal resources out of a reconfigurable platform is described. Demanding robotic vision applications in most cases require dedicated hardware for reliable operation. The designed system is based on a Cyclone IV Altera FPGA device that constitutes the main processing unit of the reconfigurable hardware and on a 32 -- bit Microchip PIC32 micro controller as a complementary processor. The main goal of this research is to accelerate image processing algorithms using only minimal resources of the custom designed reconfigurable hardware. The micro controller serves peripheral control tasks, relieving valuable resources from the FPGA device. Video images are captured using a CMOS image sensor. USB connectivity with a personal computer is provided using a FIFO-to-USB module. Operational tasks such as frame grabbing, image filtering and USB communication are integrated to the system by implementing custom-designed controllers in VHDL. Image processing functions are accelerated using a fully parallel pipeline which is described analytically. A host computer interface has also been developed in order to test the overall system in action. The system is evaluated in terms of resource usage and the advantages emanating from the proposed architecture are discussed.
Informatics, reconfigurable hardware, FPGA, parallelism, processing algorithm acceleration
J. A. Kalomiros, J. Lygouras and J. V. Vourvoulakis, "Acceleration of Image Processing Algorithms Using Minimal Resources of Custom Reconfigurable Hardware," 2012 16th Panhellenic Conference on Informatics(PCI), Piraeus, Greece Greece, 2012, pp. 68-73.