2006 IEEE International Performance Computing and Communications Conference (2006)
Phoenix, AZ, USA
Apr. 10, 2006 to Apr. 12, 2006
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/.2006.1629419
S. Hu , Networking&Comput. Syst. Group, Freescale Semicond., Inc., Austin, TX, USA
Memory bandwidth limitation is one of the major impediments to high-performance microprocessors. This paper investigates a class of store misses that can be eliminated to reduce data traffic. Those store misses fetch cache blocks whose original data is never used. If fully overwritten by subsequent stores, those blocks can be installed directly in the cache without accessing lower levels of the memory hierarchy, eliminating the corresponding data traffic. Our results indicate that for a 1 MB data cache, 28% of cache misses are avoidable across SPEC CPU INT 2000 benchmarks. We propose a simple hardware mechanism, the store fill buffer (SFB), which directly installs blocks for store misses, and substantially reduces the data traffic. A 16-entry SFB eliminates 16% of overall misses to a 64 KB data cache, resulting in 6% speedup. This mechanism enables other bandwidth-hungry techniques to further improve system performance.
bandwidth-hungry technique, modified cache block, microprocessor, data traffic, SPEC CPU INT 2000 benchmark
L. John and S. Hu, "Avoiding store misses to fully modified cache blocks," 2006 IEEE International Performance Computing and Communications Conference(PCC), Phoenix, AZ, USA, 2006, pp. 41.