The Community for Technology Leaders
Performance, Computing, and Communications Conference, 2002. 21st IEEE International (2006)
Phoenix, AZ, USA
Apr. 10, 2006 to Apr. 12, 2006
ISBN: 1-4244-0198-4
pp: 12
A. Khonsari , Dept. of Electr.&Comput. Eng., Tehran Univ., Iran
ABSTRACT
Interconnect networks employing wormhole-switching play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs, multicomputer systems and system area networks. Virtual channels greatly improve the performance of wormhole-switched networks because they reduce blocking by acting as "bypass" lanes for non-blocked messages. Capturing the effects of virtual channel multiplexing has always been a crucial issue for any analytical model proposed for wormhole-switched networks. Dally has developed a model to investigate the behaviour of this multiplexing which have been widely employed in the subsequent analytical models of most routing algorithms suggested in the literature. It is indispensable to modify Daily's model in order to evaluate the performance of channel multiplexing in more general networks where restrictions such as timing constraints of input arrivals and finite buffer size of queues are common. In this paper we consider timing constraints of input arrivals to investigate the virtual channel multiplexing problem inherent in most current networks. The analysis that we propose is completely general and therefore can be used with any interconnect networks employing virtual channels. The validity of the proposed equations has been verified through simulation experiments under different working conditions.
INDEX TERMS
routing algorithm, interconnect network, wormhole-switching, shared memory multiprocessor systems-on-chip design, MPSoC, multicomputer system, system area network, virtual channel, multiplexing
CITATION
A. Khonsari, M. Ould-Khaoua, A. Nayebi, H. Sarbazi-azad, "The impacts of timing constraints on virtual channels multiplexing in interconnect networks", Performance, Computing, and Communications Conference, 2002. 21st IEEE International, vol. 00, no. , pp. 12, 2006, doi:10.1109/.2006.1629390
80 ms
(Ver 3.3 (11022016))