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Performance, Computing, and Communications Conference, 2002. 21st IEEE International (2002)
Phoenix, AZ, USA
Apr. 3, 2002 to Apr. 5, 2002
ISBN: 0-7803-7371-5
pp: 9-15
A. Kim , Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA
This paper attempts to solve the inherently slow performance problem of Java by improving instruction level parallelism merged with a newly developed instruction folding technique. The new ILP scheme with an advanced folding mechanism creates a possibility of further improvement of instruction parallelism. A new architecture is introduced in this project by demonstrating the most recent bytecode folding mechanism followed by folded instruction level parallelism. This paper also presents a comprehensive study of branch prediction logic in the new ILP mechanism. An experiment using SPECJVM98 benchmarks reveals that as many as 7.8 bytecode instructions can be executed concurrently. In our simulation results, the 4-way parallel issue processor has achieved the highest performance, exceeding by 4 times the parallel bytecodes per issue among many other configurations. Moreover, the new ILP system proposed in this paper shows significantly higher parallelism against an existing Java ILP machine.

M. Chang and A. Kim, "Java Virtual Machine performance analysis with Java instruction level parallelism and advanced folding scheme," Performance, Computing, and Communications Conference, 2002. 21st IEEE International(PCC), Phoenix, AZ, USA, 2002, pp. 9-15.
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