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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
ISBN: 0-8186-7870-4
pp: 308
Moon-Seok Chang , Seoul National University
Kern Koh , Seoul National University
The memory system performance heavily depends on the eflciency of a translation lookaside bufSer(TLB), a cache for fast address translation. Recent trends towards multiprocessing as well as modular software structure impose more stress on TLBs, since consistency among multiple TLBs should be maintained. However, previous TLB consistency schemes do not seem suitable for large-scale multiprocessors, because they require interprocessor interrupts which are extremely harmful to the overall system performance. In this paper, we propose a lazy TLB scheme for large-scale multiprocessors. By exploiting the potential of lazy release consistency, the scheme postpones the TLB synchronization until the time of an acquire access to the shared data. This scheme allows a processor to invalidate remote TLBs asynchronously, and eliminates the need for interprocessor interrupts. Simulation results show that the lazy TLB scheme is very efficient for large-scale multiprocessors.

K. Koh and M. Chang, "Lazy TLB Consistency for Large-Scale Multiprocessors," Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on(PAS), Aizu-Wakamatsu, Fukushima, JAPAN, 1997, pp. 308.
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