Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
Shietung Peng , The University of Aizu, Fukushima, Japan
Stanislav Sedukhin , The University of Aizu, Fukushima, Japan
Igor Sedukhin , Hiwada Electronic Corp., Fukushima, Japan
A new parallel algorithm for Householder bidiagonalizaiion on parallel compulers with dynamic ring architecture is presented. The Householder bidiagonalizalion is the COR for singular value decomposition (SVD) which has been found to be very useful as an analytical tool in the presence of roundoff error and inexact dais. Two-sided Householder reduction/expansion iechnique is applzed for bidiagonalizaiion. Innovative systolic-like communication techniques are proposed which eliminate the need for computing explicitly the transpose of the matrix. Th.e experimenial study on CM-5 shows that the parallel algorithm developed in this paper achieves high speedup for large matrices.
S. Sedukhin, I. Sedukhin and S. Peng, "Householder Bidiagonalization on Parallel Computers with Dynamic Ring Architecture," Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on(PAS), Aizu-Wakamatsu, Fukushima, JAPAN, 1997, pp. 182.