The Community for Technology Leaders
Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
ISBN: 0-8186-7870-4
pp: 74
K.W. Rudd , Comput. Syst. Lab., Stanford Univ., CA, USA
M.J. Flynn , Comput. Syst. Lab., Stanford Univ., CA, USA
ABSTRACT
Recently, high performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These designs are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. We describe some of the tradeoffs between the use of static and dynamic scheduling techniques and show that with appropriate scheduling, low complexity designs using only static scheduling have significant advantages over high complexity designs using dynamic scheduling in real systems.
INDEX TERMS
parallel architectures; instruction level parallel processors; static scheduling tradeoffs; high performance computer architecture; dynamic scheduling techniques; multiple operations; low complexity designs; high complexity designs; real systems
CITATION
K.W. Rudd, M.J. Flynn, "Instruction-level parallel processors-dynamic and static scheduling tradeoffs", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 74, 1997, doi:10.1109/AISPAS.1997.581630
80 ms
(Ver 3.3 (11022016))