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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
ISBN: 0-8186-7870-4
pp: 66
Takehito Sasaki , Tohoku University.
ABSTRACT
Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architectures.
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CITATION
Takehito Sasaki, "Memory Hierarchy Design for Jetpipeline: To Execute Scalar and Vector Instructions in Parallel", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 66, 1997, doi:10.1109/AISPAS.1997.581628
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