Design of High-Performance Massively Parallel Architectures Under Pin Limitations and Non-Uniform Propagation Delay
Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
Chi-Hsiang Yeh , University of California, Santa Barbara
Behrooz Parhami , University of California, Santa Barbara
Inter-module bandwidth is one of the major constraints on the performance of current and future parallel systems. In this paper, we propose and evaluate several high-performance bus-based parallel architectures, including bus-based cyclic networks (BCNs) and quotient cyclic networks (BQCNs), which are particularly efficient in view of their respective inter-module communication patterns. The inter-cluster connection in a BCN is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degree of a basic BCN is 3; while those of BQCNs and enhanced BCNs can vary from a small constant (e.g., 2) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. A variety of algorithms can be performed efficiently on these networks, thus proving the versatility of BCNs and BQCNs.
Chi-Hsiang Yeh, Behrooz Parhami, "Design of High-Performance Massively Parallel Architectures Under Pin Limitations and Non-Uniform Propagation Delay", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 58, 1997, doi:10.1109/AISPAS.1997.581626