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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1997)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 17, 1997 to Mar. 21, 1997
ISBN: 0-8186-7870-4
pp: 50
T. Ikedo , Computer Architecture Lab. The University of Aizu
This paper proposes a new architecture for a scalable supercomputing machine, based on a distributed virtual shared memory system. The processing elements used in this system consist of an ASIC embedding 5 PE, 20 floating point multipliers, 15 adders, and one divider and square root arithmetic unit in a single chip. The 5 PE are interconnected with a complete graph. The reconfigurable architecture is designed for dynamic high-performance applications like virtual reality or multimedia systems. One chip implements a cluster, and an inter-cluster network can be established through a multiple interconnection network of these chips. It has 3.0~Gflops/chip as hardware peak performance, and can be scaled by an optical link via a specified router.

T. Ikedo, "An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network," Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on(PAS), Aizu-Wakamatsu, Fukushima, JAPAN, 1997, pp. 50.
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