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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1995)
Aizu-Wakamatsu, Fukushima, Japan
Mar. 15, 1995 to Mar. 17, 1995
ISBN: 0-8186-7038-X
pp: 287
B.P. Herndon , Integrated Circuits Lab., Stanford Univ., CA, USA
A. Raefsky , Integrated Circuits Lab., Stanford Univ., CA, USA
R.W. Dutton , Integrated Circuits Lab., Stanford Univ., CA, USA
ABSTRACT
The paper presents a methodology for adapting dusty deck PDE solvers for parallel execution. Our approach minimizes changes to existing code and data structures, thereby preserving the value captured within dusty decks. This scheme uses the single program multiple data programming paradigm on message passing distributed memory architectures. To demonstrate the viability of our methodology the commercially available, dusty deck semiconductor device modeling program, PISCES, has been adapted for parallel execution. Simulating realistic complex device structures, we have achieved excellent performance gains over high performance serial workstations. Also, the scalability of the parallel simulator allows the simulation of structures too large for our existing serial computers.
INDEX TERMS
message passing; distributed memory systems; data structures; digital simulation; partial differential equations; PDE solver; PISCES-MP; dusty deck PDE solvers; parallel execution; data structures; single program multiple data programming paradigm; message passing distributed memory architectures; dusty deck semiconductor device modeling program; realistic complex device structures; parallel simulator
CITATION
B.P. Herndon, A. Raefsky, R.W. Dutton, "Parallelizing a PDE solver: experiences with PISCES-MP", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 287, 1995, doi:10.1109/AISPAS.1995.401327
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