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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1995)
Aizu-Wakamatsu, Fukushima, Japan
Mar. 15, 1995 to Mar. 17, 1995
ISBN: 0-8186-7038-X
pp: 153
V. Obac Roda , Inst. de Fisica e Quimica de Sao Carlos, Sao Paulo Univ., Brazil
T.T.Y. Lin , Inst. de Fisica e Quimica de Sao Carlos, Sao Paulo Univ., Brazil
ABSTRACT
We investigated some reconfiguration and routing aspects of fault tolerant processing arrays. An interconnection topology with disjoint buses for the horizontal and vertical connections, called "double bus array", was adopted. Reconfiguration of the array after diagnosis encompasses the allocation of spare units to replace the faulty processors, renaming of the processor elements and interconnecting (routing) data through the operating processors according to the initial specified operation. We fully simulated reconfiguration and routing for arrays of size N, from 5 to 25 processors and faults from 1 to 2N+1. Faults were generated randomly to simulate defects on a wafer. We present the results of the simulations and discuss the possible reasons for reliability improvements.
INDEX TERMS
reconfigurable architectures; fault tolerant computing; reliability; arrays; multiprocessor interconnection networks; system buses; virtual machines; spare positioning; reconfigurability; two-dimensional processor arrays; routing aspects; fault tolerant processing arrays; interconnection topology; disjoint buses; vertical connections; horizontal connections; double bus array; spare unit allocation; faulty processor replacement; processor element renaming; operating processors; initial specified operation; simulation; randomly generated faults; wafer; reliability improvements
CITATION
V. Obac Roda, T.T.Y. Lin, "On the effect of spare positioning on the reconfigurability of two-dimensional processor arrays", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 153, 1995, doi:10.1109/AISPAS.1995.401343
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