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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1995)
Aizu-Wakamatsu, Fukushima, Japan
Mar. 15, 1995 to Mar. 17, 1995
ISBN: 0-8186-7038-X
pp: 130
V. Marakhovsky , Aizu Univ., Japan
V. Varshavsky , Aizu Univ., Japan
Tam-Anh Chu , Aizu Univ., Japan
The problem of global synchronization is solved for asynchronous processor arrays and multiprocessor systems with an arbitrary interconnection graph. Global synchronization of asynchronous systems is treated as a homomorphic mapping of an asynchronous system behavior in logical time onto the behavior of the corresponding synchronous system with a common clock functioning in physical time. The solution is based on decomposing the system to the processor stratum and synchro-stratum; the latter plays the role of a global asynchronous clock. For the case of a synchronous system with two-phase master-slave synchronization, a simple implementation of the synchro-stratum for the corresponding asynchronous system is proposed. It is shown that, depending on the local behavior of the processors, the synchro-stratum is able to perform two types of global synchronization: parallel synchronization and synchronization that uses a system of synchro-waves.
synchronisation; timing; concurrency control; multiprocessor interconnection networks; performance evaluation; parallel architectures; parallel algorithms; graph theory; logical timing; global synchronization; asynchronous arrays; asynchronous processor arrays; multiprocessor systems; arbitrary interconnection graph; homomorphic mapping; asynchronous system behavior; logical time; common clock; processor stratum; synchro-stratum; global asynchronous clock; two-phase master-slave synchronization; parallel synchronization; synchro-waves
V. Marakhovsky, V. Varshavsky, Tam-Anh Chu, "Logical timing (global synchronization of asynchronous arrays)", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 130, 1995, doi:10.1109/AISPAS.1995.401346
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