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Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on (1995)
Aizu-Wakamatsu, Fukushima, Japan
Mar. 15, 1995 to Mar. 17, 1995
ISBN: 0-8186-7038-X
pp: 2
T.L. Kunii , Sch. of Comput. Sci. & Eng., Aizu Univ., Japan
S. Nishimura , Sch. of Comput. Sci. & Eng., Aizu Univ., Japan
ABSTRACT
This paper describes a parallel polygon rendering method on the graphics computer VC-1. The architecture of the VC-1 is a loosely-coupled array of general-purpose processors, each of which is equipped with a local frame buffer. The contents of the local frame buffers are merged into one in real time considering the visibility control based on screen depth. In our polygon rendering method, polygons are distributed among the processors and each processor independently computes the image of the assigned polygons using the Z-buffer method. To achieve load balancing, a technique called adaptive parallel rasterization is developed. The adaptive parallel rasterization automatically selects the appropriate parallelizing approach according to the estimated size of polygons displayed on the screen. The measured rendering performance of VC-1 using this polygon rendering method is shown.
INDEX TERMS
rendering (computer graphics); computational geometry; special purpose computers; parallel machines; parallel architectures; real-time systems; resource allocation; software performance evaluation; parallel polygon rendering; graphics computer; VC-1; loosely-coupled array; general-purpose processors; local frame buffer; real time; visibility control; screen depth; polygon rendering method; assigned polygons; Z-buffer method; load balancing; adaptive parallel rasterization; measured rendering performance
CITATION
T.L. Kunii, S. Nishimura, "Parallel polygon rendering on the graphics computer VC-1", Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on, vol. 00, no. , pp. 2, 1995, doi:10.1109/AISPAS.1995.401361
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