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2011 Sixth International Symposium on Parallel Computing in Electrical Engineering (2011)
Luton, United Kingdom
Apr. 3, 2011 to Apr. 7, 2011
ISBN: 978-0-7695-4397-0
pp: 173-178
ABSTRACT
The implementation of complex signal processing algorithms are required to achieve robust transmission, whereas mobile wireless application require low power dissipation. This paper describes an algorithm and a corresponding hardware architecture for the implementation of OFDMA 802.16e channel estimation. The advantage of the proposed architecture are low power and efficient resource utilization since we use iterative memory shared architecture that exploits reutilization of the processor elements and memory units. The higher data access scheme is utilized by scheduled memory sharing with common bus. Furthermore, we increase parallel efficiency by folding the architecture to reduce the number of processor elements.
INDEX TERMS
channel estimation, OFDMA, mobile WiMAX
CITATION

T. Adiono, Iskandar, A. Kurniawan and S. Galih, "Folding Memory Shared Processor Array (FMSPA) Architecture for Channel Estimation of Downlink OFDMA IEEE 802.16e System," 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Luton, United Kingdom, 2011, pp. 173-178.
doi:10.1109/PARELEC.2011.25
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