Exploration of Tasks Partitioning between Hardware Software and Locality for a Wireless Camera Based Vision Sensor Node
2011 Sixth International Symposium on Parallel Computing in Electrical Engineering (2011)
Luton, United Kingdom
Apr. 3, 2011 to Apr. 7, 2011
In this paper we have explored different possibilities for partitioning the tasks between hardware, software and locality for the implementation of the vision sensor node, used in wireless vision sensor network. Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate on one dimensional data, wireless vision sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. The research focus within the field of wireless vision sensor networks have been on two different assumptions involving either sending raw data to the central base station without local processing or conducting all processing locally at the sensor node and transmitting only the final results. Our research work focus on determining an optimal point of hardware/software partitioning as well as partitioning between local and central processing, based on minimum energy consumption for vision processing operation. The lifetime of the vision sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of FPGA and micro controller for the implementation of the vision sensor node. Our results show that sending compressed images after pixel based tasks will result in a longer battery life time with reasonable hardware cost for the vision sensor node.
Wireless Vision Sensor Networks, Vision Sensor Node, Hardware/Software Partioning, Reconfigurable Architecture, Image Processing
K. Khursheed, M. Imran, B. Thörnberg, N. Lawal, A. W. Malik and M. O'Nils, "Exploration of Tasks Partitioning between Hardware Software and Locality for a Wireless Camera Based Vision Sensor Node," 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Luton, United Kingdom, 2011, pp. 127-132.