2011 Sixth International Symposium on Parallel Computing in Electrical Engineering (2011)
Luton, United Kingdom
Apr. 3, 2011 to Apr. 7, 2011
The emergence of the third dimension in Network-on-Chip (NoC) design as a quest to improve the quality of service (QoS) of on-chip communication has evolved with enormous interest. However the underlying router architecture of 3D NoCs have more area footprint than 2D routers. In this paper, we investigate heterogeneous 3D NoC topologies with the focus on finding a balance between the manufacturing cost and the QoS by employing the area and performance benefits provided by 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topology. Experimental results show a negligible penalty in throughput of 3D mesh with homogeneous distribution of 3D NoC-bus hybrid routers. The heterogeneity however provides superiority in area efficiency of the NoC resources.
A. Ahmadinia and M. O. Agyeman, "Optimising Heterogeneous 3D Networks-on-Chip," 2011 Sixth International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Luton, United Kingdom, 2011, pp. 25-30.