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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 392-395
G. Rubin , Bialystok Technical University, Poland
K. Bielawski , Bialystok Technical University, Poland
J. Baszun , Bialystok Technical University, Poland
This paper consider a hardware implementation of adaptive Infinite Impulse Response filtering where a Genetic Algorithm is used to adapting the filter weights. A unique genetic algorithm is developed to optimize filter coefficients in adaptation process. Hardware architecture and its behaviour at simulations for DE Jong test function was presented as well differences in interconnections with high speed IIR filter with coefficient values as a input to the filter realization. Proposed design of hardware realization of adaptive IIR filter is limited to second order filter.

G. Rubin, K. Bielawski and J. Baszun, "A Hardware Conceptual Prototyping of the Genetic Algorithm to Adaptive IIR Filtering," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 392-395.
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