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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 386-391
Awni Itradat , Concordia University, Canada
M.O. Ahmad , Concordia University, Canada
Ali Shatnawi , Jordan University of Science and Technology, Jordan
ABSTRACT
This paper presents a novel technique to obtain time schedules for cyclic DFGs representing DSP algorithms mapped onto multiprocessor systems with non-negligible inter-processor communication delays. In this paper, the question of optimizing the input/output delay in the present of inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd- Warshall's longest path algorithm so that the interprocessor communication overhead is taken into consideration to provide an optimal schedule.
INDEX TERMS
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CITATION

A. Itradat, M. Ahmad and A. Shatnawi, "A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 386-391.
doi:10.1109/PARELEC.2006.2
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