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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 380-385
Grzegorz Pastuszak , Warsaw University of Technology, Poland
The number of clock cycles sacrificed to process binary symbols in hardware entropy coders may limit the performance of the whole H.264/AVC coder. This paper describes enhancements of the architecture based on the parallel symbol encoding. Five versions of the architecture are described to study the area/performance trade-off. The implementation results show that the parallel symbol encoding allows higher efficiency expressed as the area/performance ratio.

G. Pastuszak, "Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 380-385.
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