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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 374-379
Michael Schmidt , Friedrich-Schiller-University, Germany
Andreas Loos , Friedrich-Schiller-University, Germany
Dietmar Fey , Friedrich-Schiller-University, Germany
Due to the increasing needs of always faster automation technology in the field of industrial fabrication the common methods of machine vision meet their limits. The reasons are the widely used serial computation and transmission of data streams on the base of strict spatially separated data capturing by an image sensor and data processing, e.g. by a coupled DSP. To meet serious real time requirements many discrete high speed components are used which often causes high costs. In contrast we propose a 3D architecture based on stacked chip dies. In order to find a trade-off between speed and required chip area we present a space-time multiplex architecture, i.e. clusters of pixels are processed time-serially by one processor and several clusters are processed by a multi-core processor. Our architecture allows the successive computation of basic low-level image processing operations. We determined an optimal number of serially processed pixels between 16 and 32 in a cluster for a resolution of 256?256 pixels. Furthermore we found out that the most efficient way is to process a line based cluster.

A. Loos, M. Schmidt and D. Fey, "A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 374-379.
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