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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 363-368
M.P. Malumbres , Miguel Hernandez University, Spain
A. Gonz?lez , Technical University of Valencia, Spain
A. Rodr?guez , Technical University of Valencia, Spain
ABSTRACT
Last generation video encoding standards increase computing demands in order to reach the limits on compression efficiency. This is particularly the case of H.264/AVC specification that is gaining interest in industry. We are interested in applying parallel processing to H.264 encoders in order to fulfill the computation requirements imposed by stressing applications like video on demand, videoconference, live broadcast, etc. Given a delivered video quality and bit rate, the main complexity parameters are image resolution, frame rate and latency. These parameters can still be pushed forward in such a way that special purpose hardware solutions are not available. Parallel processing based on off-the-shelf components is a more flexible general purpose alternative. In this work we propose a hierarchical parallelization of H.264 encoders very well suited to low cost clusters. Our proposal uses MPI message passing parallelization at two levels: GOP and frame. The GOP level encodes simultaneously several groups of consecutive frames and the frame level encodes in parallel several slices of one frame. In previous work we found that GOP parallelism alone gives good speed-up but imposes very high latency, on the other side frame parallelism gets less efficiency but low latency. Combining both approaches we obtain a compromise between speed-up and latency and then a broader spectrum of applications can be covered.
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CITATION
M.P. Malumbres, A. Gonz?lez, A. Rodr?guez, "Hierarchical Parallelization of an H.264/AVC Video Encoder", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 363-368, 2006, doi:10.1109/PARELEC.2006.42
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