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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 220-226
Jacek Pierzchlewski , Poznan University of Technology, Poland
Pawel Sniatala , Poznan University of Technology, Poland
Blazej Nowakowski , Poznan University of Technology, Poland
Andrzej Rybarczyk , Poznan University of Technology, Poland
Wojciech Wencel , Poznan University of Technology, Poland
This paper presents prototype board and its operating system dedicated for application specific parallel processing. The proposed architecture consists of two AVR microprocessors, FPGA Spartan3, SRAM and Flash EEPROM Memories, DA converters, and several serial communication ports. To make the system "designer friendly" a supervising algorithm, which can be called as a kind of "operating system" was elaborated. The algorithms were described in VHDL. The Spartan3 FPGA was chosen as a target platform to implement the master controller for the system. Necessary IO devices? controllers were implemented in AVRmicro. The designed board with elaborated libraries provides convenient solution to develop dedicated parallel processing systems.

A. Rybarczyk, P. Sniatala, J. Pierzchlewski, W. Wencel and B. Nowakowski, "FPGA Chip as a System Master for Hardware Aided Parallel Computing," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 220-226.
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