The Community for Technology Leaders
Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 208-213
Oleg Maslennikow , Technical University of Koszalin, Poland
Anatolij Sergiyenko , National Technical University of Ukraine, Ukraine
A method of mapping DSP algorithms into FPGA devices is considered. Algorithms are represented by synchronous data flow graphs, and are mapped into pipelined data path. The method consists of placing the algorithm graph in the multidimensional index space and mapping it into structure and event subspaces. The special limitations, which are injected to the mapping process, minimize both clock time and hardware volume including multiplexer inputs.

O. Maslennikow and A. Sergiyenko, "Mapping DSP Algorithms into FPGA," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 208-213.
88 ms
(Ver 3.3 (11022016))