Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations
Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Sept. 13, 2006 to Sept. 17, 2006
Alexander A. Petrovsky , Bialystok Technical University, Poland
Sergei L. Shkredov , Belarusian State University of Informatics and Radioelectronics, Russia
The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGAaware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count, area, power dissipation). The considered design examples prove method's good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered.
S. L. Shkredov and A. A. Petrovsky, "Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 181-186.