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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 181-186
Sergei L. Shkredov , Belarusian State University of Informatics and Radioelectronics, Russia
Alexander A. Petrovsky , Bialystok Technical University, Poland
ABSTRACT
The results presented in the article are based on a methodology for automatic synthesis of real-time split radix 2-4 parallel-pipeline FFT-processors at structural level. The approach is oriented at reconfigurable FPGAaware design and allows taking into account real-time application restrictions (input data structure and format, operating frequency, transform size, overall throughput) as well as other design restrictions (CLB-count, area, power dissipation). The considered design examples prove method's good abilities for hardware optimization. Variants of split radix 2-4 computing element implementation are compared. Switching over from floating point arithmetics to fixed point data and the corresponding accuracy issues are considered.
INDEX TERMS
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CITATION
Sergei L. Shkredov, Alexander A. Petrovsky, "Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 181-186, 2006, doi:10.1109/PARELEC.2006.18
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