Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Sept. 13, 2006 to Sept. 17, 2006
Hritam Dutta , University of Erlangen-Nuremberg, Germany
Frank Hannig , University of Erlangen-Nuremberg, Germany
J?urgen Teich , University of Erlangen-Nuremberg, Germany
Processor arrays are used as accelerators for plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor array architectures has lead to demand for mapping tools to realize the full potential of these architectures. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor array apart from different levels of cache arrays have a number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. In this paper, we introduce for the first time a detailed methodology encompassing hierarchical partitioning.
H. Dutta, F. Hannig and J. Teich, "Hierarchical Partitioning for Piecewise Linear Algorithms," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 153-160.