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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 139-144
T. Srinivasan , Sri Venkateswara College of Engineering, India
N. Dhanasekar , Sri Venkateswara College of Engineering, India
M. Nivedita , Sri Venkateswara College of Engineering, India
R. Dhivyakrishnan , Sri Venkateswara College of Engineering, India
A.A. Azeezunnisa , Sri Venkateswara College of Engineering, India
The internet traffic gets exploded due to the increasing demand for bandwidth as more number of users gets added to the internet. In order to meet the demands of the growing needs, the working of various devices and operations has to be redesigned. One of the areas is the design of the high performance router. The traditional router performs two basic tasks in forwarding a packet. Firstly, looking up the packet?s destination address in the router?s database and secondly, switching the packet to one or more of the outgoing links. The classification of packets at the router based upon multiple fields is called as packet classification. In this paper, we propose an Aggregate Bit Vector Packet Classification using Prefix Computation Model (ABVPC using PCM) which combines the effect of both scalability and parallelization. It is aimed at overcoming the defects of the existing ABV algorithms. Simulation Results illustrate that the folding technique using PCM significantly improves the performance.

M. Nivedita, A. Azeezunnisa, R. Dhivyakrishnan, N. Dhanasekar and T. Srinivasan, "Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 139-144.
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