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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 89-94
Jan M? , Dresden University of Technology, Germany
In this paper we introduce a generalised resource model for parallel instruction scheduling. This model is used to formulate the resource constraints for periodic loop schedules, which are then rewritten employing an efficient flow graph model. <p>The generalisation leads to a significant simplification and acceleration of the painful process of modelling new resource classes, and of incorporating specific processor features. Moreover, the model grants an accurate representation of the processor resources. We illustrate these properties at the examples of functional units and processor registers.</p>

J. M?, "Generalised Resource Model for Parallel Instruction Scheduling," International Symposium on Parallel Computing in Electrical Engineering(PARELEC), Bialystok, 2006, pp. 89-94.
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