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Parallel Computing in Electrical Engineering, 2004. International Conference on (2006)
Bialystok, Poland
Sept. 13, 2006 to Sept. 17, 2006
ISBN: 0-7695-2554-7
pp: 62-67
Henryk Krawczyk , Technical University of Gda?sk, Poland
Tomasz Madajczak , Technical University of Gda?sk, Poland
ABSTRACT
This document presents the concept of integrating the SHECS (Shared Explicit Cache System)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (Thread-Level Parallelism - Chip Multiprocessing) SMP (Symmetric Multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with Software Multi- Queue SMP Scheduler, the second integrates the SHECSbased CS with Hardware Multi-Queue SMP Scheduler implemented as an additional functional unit within the TLP-CMP. The both propositions are implemented and simulated with using SoC (System-on-Chip) such as Intel? IXP 2800 network processor. The results of proveof- concept simulation (obtained with the IXA SDK 4.2 Workbench simulation environment) are presented and discussed in this document.
INDEX TERMS
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CITATION
Henryk Krawczyk, Tomasz Madajczak, "Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 62-67, 2006, doi:10.1109/PARELEC.2006.45
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