The Community for Technology Leaders
Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Dresden, Germany
Sept. 7, 2004 to Sept. 10, 2004
ISBN: 0-7695-2080-4
TABLE OF CONTENTS

Reviewers (PDF)

pp. xvi

Sponsors (PDF)

pp. xvii
Invited Talks

The Role of Parallel Computing at ABB Corporate Research Switzerland (PDF)

Andreas Blaszczyk , ABB Corporate Research Baden-Daettwil, Switzerland
pp. 4
Session A1: Parallel System Architectures I

Optimising MPI Applications for Heterogeneous Coupled Clusters with MetaMPICH (Abstract)

Carsten Clauss , RWTH Aachen University, Germany
Martin P?ppe , RWTH Aachen University, Germany
Thomas Bemmerl , RWTH Aachen University, Germany
pp. 7-12

Matrix Multiplication Performance on Commodity Shared-Memory Multiprocessors (Abstract)

M. Fleury , University of Essex, UK
G. Tsilikas , University of Essex, UK
pp. 13-18

Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm (Abstract)

Marek Tudruj , Polish-Japanese Institute of Information Technology, Warsaw, Poland; Polish Academy of Sciences, Poland
Adam Smyk , Polish-Japanese Institute of Information Technology, Warsaw, Poland
pp. 19-24

Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements (Abstract)

Tomasz Madajczak , Technical University of Gdansk, Poland
Henryk Krawczyk , Technical University of Gdansk, Poland
pp. 25-30
Session B1: Design and Design Automation I

Large-Scale Tolerance Analysis (Abstract)

Dirk Fimmel , Dresden University of Technology
Wolfgang Schwarz , Dresden University of Technology
Stefan Quitzk , Dresden University of Technology
pp. 33-38

Employing Compilers for Determining Architectural Features of Application-Specific DSPs (Abstract)

Michael Hosemann , Dresden University of Technology, Germany
Gerhard P. Fettweis , Dresden University of Technology, Germany
Jie Guo , Dresden University of Technology, Germany
pp. 39-44

Compiler Scheduling for STA-Processors (Abstract)

Gordon Cichon , Technische Universit?t, Dresden
P. Robelly , Technische Universit?t, Dresden
H. Seidel , Technische Universit?t, Dresden
M. Bronzel , Technische Universit?t, Dresden
Gerhard Fettweis , Technische Universit?t, Dresden
pp. 45-60

An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation (Abstract)

Daniel Matolin , Dresden University of Technology, Germany
Stefan Getzlaff , Dresden University of Technology, Germany
Ren? Sch? , Dresden University of Technology, Germany
J? Schreiter , Dresden University of Technology, Germany
pp. 51-55
Session A2: Methods for Parallelization

Moldable Task Scheduling in Dynamic SMP Clusters with Communication on the Fly (Abstract)

Gregory Mounie , IMAG - France
Lukasz Masko , Institute of Computer Science of the Polish Academy of Sciences, Poland
Marek Tudruj , Institute of Computer Science of the Polish Academy of Sciences, Poland; Polish-Japanese Institute of Information Technology, Poland
Denis Trystram , IMAG - France
pp. 59-64
Session B2: Methods for Automatic Parallelization

Dynamic Piecewise Linear/Regular Algorithms (Abstract)

J? Teich , University of Erlangen-Nuremberg, Germany
Frank Hannig , University of Erlangen-Nuremberg, Germany
pp. 79-84

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays (Abstract)

Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
pp. 85-90

A Modified Vertex Method for Parallelization of Arbitrary Nested Loops (Abstract)

W. Bielecki , Technical University of Szczecin, Poland
R. Kocisz , Technical University of Szczecin, Poland
pp. 91-96
Session A3: Specification and Modeling of Parallel Systems

A PC-Based Real-Time Parallel Simulator of Electric Systems and Drives (Abstract)

Jean B?langer , Opal-RT Technologies inc., Canada
Christian Dufour , Opal-RT Technologies inc., Canada
pp. 105-113

Using ModelSim, Matlab/Simulink and NS for Simulation of Distributed Systems (Abstract)

Sven Altmann , Fraunhofer Institute for Integrated Circuits, Germany
Uwe Hatnik , Fraunhofer Institute for Integrated Circuits, Germany
pp. 114-119
Session B3: Parallel System Architectures II

A New Memory Module for Memory Intensive Applications (Abstract)

Yasunori Dohi , Yokohama National University
Hirotaka Hakozaki , Yokohama National University
Noboru Tanabe , Toshiba
Hideharu Amano , Keio University
Masasige Nakatake , Yokohama National University
Hironori Nakajo , Tokyo University of Agriculture and Technology
pp. 123-128

Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express (Abstract)

Jose Ignacio Gomez , Universidad Complutense de Madrid, Spain
Kurt Keutzer , University of California, Berkeley
Christian Sauer , Infineon Technologies, Munich, Germany
Matthias Gries , University of California, Berkeley
Scott Weber , University of California, Berkeley
pp. 129-134

Implementation of the Massively Parallel Model GCA (Abstract)

Wolfgang Heenes , Technische Universit?t Darmstadt
Rolf Hoffmann , Technische Universit?t Darmstadt
Mathias Halbach , Technische Universit?t Darmstadt
pp. 135-139
Session A4: Numerical Methods for Parallel Processing I

The Parallel Computations for the Linear State Equations (Abstract)

Pawel Myszkowski , Bialystok Technical University, Poland
Konrad Radzik , Polish-Japanese Institute of Information Technology
Andrzej Jordan , Bialystok Technical University, Poland
pp. 143-145

Computing Passive Reduced-Order Models for Circuit Simulation (Abstract)

Enrique S. Quintana-Ort? , Universidad Jaume I, Spain
Peter Benner , Technische Universit?t Chemnitz, Germany
Gregorio Quintana-Ort? , Universidad Jaume I, Spain
pp. 146-151

Visualization of the Parallel Finite-Difference Time-Domain Method Computations Results (Abstract)

Andrzej Jordan , Bialystok Technical University, Poland
Adam Skorek , Universit? du Qu?bec ? Trois-Rivi?res, Canada
Wojciech Walendziuk , Bialystok Technical University, Poland
pp. 152-155

Parallel Tabu Search Method Approach for Very Difficult Permutation Scheduling Problems (Abstract)

Mieczyslaw Wodecki , University of Wroclaw, Poland
Wojciech Bozejko , Wroclaw University of Technology, Poland
pp. 156-161
Session B4: Reconfigurable Computing I

Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture (Abstract)

Pil Woo Chun , Ryerson University Toronto, Canada
Vadim Geurkov , Ryerson University Toronto, Canada
Irina Terterian , Ryerson University Toronto, Canada
Lev Kirischian , Ryerson University Toronto, Canada
pp. 165-170

A Design Environment for Processor-Like Reconfigurable Hardware (Abstract)

T. Kuhn , University of Tuebingen, Germany
T. Oppold , University of Tuebingen, Germany
W. Rosenstiel , University of Tuebingen, Germany
T. Schweizer , University of Tuebingen, Germany
pp. 171-176

Dynamically Reconfigurable Hardware for Object-Oriented Processing (Abstract)

Sorin A. Huss , Darmstadt University of Technology
Andreas K? , Darmstadt University of Technology
pp. 181-186
Session A5: Numerical Methods for Parallel Processing II

The Modified Speculative Method for the Transient States Analysis (Abstract)

Jaroslaw Forenc , Bialystok Technical University, Poland
Andrzej Jordan , Polish-Japanese Institute of Information Technology, Poland
pp. 189-193

Limits of the Distributed Finite Element Time Domain Algorithm in Multi-Computer Environment (Abstract)

Christian Vollaire , Ecole Centrale de Lyon, France
Boguslaw Butrylo , Bialystok Technical University, Poland
Laurent Nicolas , Ecole Centrale de Lyon, France
pp. 194-199
Session B5: Embedded Multiprocessors (and Network Processors)

Network Application Driven Instruction Set Extensions for Embedded Processing Clusters (Abstract)

Michael Thies , University of Paderborn, Germany
Ulrich R?ckert , University of Paderborn, Germany
Adrian Slowik , University of Paderborn, Germany
Dinh Khoi Le , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
Matthias Gr?newald , University of Paderborn, Germany
J?rg-Christian Niemann , University of Paderborn, Germany
Uwe Kastens , University of Paderborn, Germany
pp. 209-214

A Parallel Hardware-Software System for Signal Processing Algorithms (Abstract)

Rainer Schaffer , Dresden University of Technology, Germany
Mathias Kortke , Dresden University of Technology, Germany
Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
Jan M? , Dresden University of Technology, Germany
J?rgen Kelber , University of Applied Sciences Schmalkalden, Germany
pp. 215-220

Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver (Abstract)

G. Cichon , TU-Dresden, Germany
M. Bronzel , TU-Dresden, Germany
P. Robelly , TU-Dresden, Germany
H. Seidel , TU-Dresden, Germany
G. Fettweis , TU-Dresden, Germany
pp. 221-225
Session A6: Fault-Tolerant and Evolutionary Systems

Parallel Genetic Algorithms for Third Generation Mobile Network Planning (Abstract)

Liang Guo , University of Luton, UK
Carsten Maple , University of Luton, UK
Jie Zhang , University of Luton, UK
pp. 229-236

A Fault-Tolerant Voting Scheme for Multithreaded Environments (Abstract)

Bernhard Fechner , FernUniversit?t Hagen
J?rg Keller , FernUniversit?t Hagen
pp. 237-239

Tuning of Parallel ROI Matching Algorithms (Abstract)

Henryk Krawczyk , Gdansk University of Technology, Poland
Jamil Saif , Gdansk University of Technology, Poland
pp. 246-248
Session B6: Reconfigurable Computing II

Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips (Abstract)

Lutz Hoppe , Friedrich-Schiller-University Jena, Germany
Dietmar Fey , Friedrich-Schiller-University Jena, Germany
Andreas Loos , Friedrich-Schiller-University Jena, Germany
pp. 251-255
Session A7: Parallel Software Environments I

The Cellular Automata Network Compiler System: Modules and Features (Abstract)

C. R. Calidonna , Istituto di Cibernetica "E. Caianiello" C.N.R, Italy
M. Mango Furnari , Istituto di Cibernetica "E. Caianiello" C.N.R, Italy
pp. 271-276

Providing a High-Performance VIA-Module for LAM/MPI (Abstract)

Tobias Wenzel , Chemnitz University of Technology, Germany
Torsten Mehlan , Chemnitz University of Technology, Germany
Ralph Engler , Chemnitz University of Technology, Germany
Wolfgang Rehm , Chemnitz University of Technology, Germany
pp. 277-282

An EM Algorithm for Fitting of Real Traffic Traces to PH-Distribution (Abstract)

Peter Buchholz , Dortmund University, Germany
Andriy Panchenko , Dresden University of Technology, Germany
pp. 283-288

FIT - A Parallel Hierarchical Fault Simulation Environment (Abstract)

Heinrich Theodor Vierhaus , Brandenburg University of Technology Cottbus
Silvio Misera , Brandenburg University of Technology Cottbus
pp. 289-294
Session B7: Real Time Parallel Computing I

Associative Graph Processor and Its Properties (Abstract)

Anna Nepomniaschaya , Institute of Computational Mathematics and Mathematical Geophysics, Russia
Zbigniew Kokosinski , Cracow University of Technology, Poland
pp. 297-302

Hardware Accelerated Data Analysis (Abstract)

Mario Porrmann , University of Paderborn, Germany
Marc Franzmeier , University of Paderborn, Germany
Ulrich R?ckert , University of Paderborn, Germany
Christopher Pohl , University of Paderborn, Germany
pp. 309-314

Communication Analysis for Network-on-Chip Design (Abstract)

A. Siebenborn , FZI Forschungszentrum Informatik, Germany
O. Bringmann , FZI Forschungszentrum Informatik, Germany
W. Rosenstiel , Universit?t T?bingen, Germany
pp. 315-320
Session A8: Parallel Software Environments II

Co-Ordination of Parallel GRID Applications using Synchronizers (Abstract)

J. Borkowski , Polish-Japanese Institute of Information Technology, Poland
D. Kopanski , Polish-Japanese Institute of Information Technology, Poland
M. Tudruj , Polish-Japanese Institute of Information Technology, Poland; Polish Academy of Sciences, Poland
pp. 323-327

Parallel Program Control Based on Hierarchically Detected Consistent Global States (Abstract)

Janusz Borkowski , Polish-Japanese Institute for Information Technology, Warsaw, Poland
pp. 328-333
Session B8: Real Time Parallel Computing II

A Tool for Exploring the Large Scale Signal Processing Systems Specification (Abstract)

Martijn van Veelen , ASTRON, Netherlands
Laurentiu Nicolae , Leiden University, Netherlands
Sylvain Alliot , ASTRON, Netherlands
pp. 341-348

Using Switched Ethernet for Hard Real-Time Communication (Abstract)

Hermann Haertig , TU Dresden, Germany
Jork Loeser , TU Dresden, Germany
pp. 349-353

Performance Evaluation of Parallel MPEG-4 Video Coding Algorithms on Clusters of Workstations (Abstract)

M. P. Malumbres , Technical University of Valencia, Spain
A. Rodriguez , Technical University of Valencia, Spain
A. Gonz?lez , Technical University of Valencia, Spain
pp. 354-357
Posters

Loop Scheduling for Multithreaded Processors (Abstract)

Georgios Dimitriou , University of Thessaly, Volos, Greece
Constantine Polychronopoulos , University of Illinois at Urbana-Champaign
pp. 361-366

Influence of Exception Handling on Distributed Applications (Abstract)

Pawel L. Kaczmarek , Gdansk University of Technology, Poland
Henryk Krawczyk , Gdansk University of Technology, Poland
pp. 367-371

Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach (Abstract)

J. P. Robelly , Dresden University of Technology, Germany
G. Fettweis , Dresden University of Technology, Germany
G. Cichon , Dresden University of Technology, Germany
H. Seidel , Dresden University of Technology, Germany
pp. 372-375

Dynamic Reconfiguration of Real-Time Network Interfaces (Abstract)

Ulrich R?ckert , University of Paderborn, Germany
Bj?rn Griese , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
Erik Vonnahme , University of Paderborn, Germany
pp. 376-379

Digital Electromagnetic Model of the Power System: Parallel Implementation for Multicomputers (Abstract)

I. Naumkin , Russian Academy of Sciences
N. Malyshkin , Russian Academy of Sciences
V. Korneev , Russian Academy of Sciences
V. Malyshkin , Russian Academy of Sciences
M. Ostapkevich , Russian Academy of Sciences
pp. 380-385

Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly (Abstract)

Lukasz Masko , Institute of Computer Science of the Polish Academy of Sciences
Marek Tudruj , Institute of Computer Science of the Polish Academy of Sciences; Polish-Japanese Institute of Information Technology
pp. 386-389

Towards Easy-to-Use Checkpointing of MPI Applications within CLUSTERIX (Abstract)

Arkadiusz Urbaniak , Gdansk University of Technology, Poland
Pawel Czarnul , Gdansk University of Technology, Poland
Maciej Dyczkowski , Wroclaw University of Technology
Marcin Fraczak , Gdansk University of Technology, Poland
Bartlomiej Balcerek , Wroclaw University of Technology
pp. 390-393

Distributed Genetic Algorithm for Finding Fuzzy Rational Approximators (Abstract)

Octavian Buzatu , Institute of Theoretical Computer Science, Romania
Octav Brudaru , Technical University "Gh. Asachi" Iasi, Romania
pp. 394-397

Scheduling Byte Code-Defined Data Dependence Graphs of Object Oriented Programs (Abstract)

Eryk Laskowski , Institute of Computer Science PAS, Warsaw, Poland
Richard Olejnik , Universit? des Sciences et Technologies de Lille
Marek Tudruj , Institute of Computer Science PAS, Warsaw, Poland
Bernard Toursel , Universit? des Sciences et Technologies de Lille
pp. 398-401

Author Index (PDF)

pp. 403-404
88 ms
(Ver 3.1 (10032016))