Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.33
Marek Tudruj , Institute of Computer Science of the Polish Academy of Sciences; Polish-Japanese Institute of Information Technology
Lukasz Masko , Institute of Computer Science of the Polish Academy of Sciences
This paper presents a new version of the dynamic SMP cluster -based architecture oriented towards networks on chip implementation technique. Smaller sub-networks with many dynamic SMP clusters and communication on the fly are connected by a central global network. Processors are provided with multi-ported data caches that enable parallel data transactions with memory modules, including parallel data pre-fetching and communication on the fly. Simulation experiments are described, based on a graph program representation and an automatic graph evaluator. They show efficiency of the proposed solution for very fine grain numerical problems.
L. Masko and M. Tudruj, "Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 386-389.