Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.19
A. Siebenborn , FZI Forschungszentrum Informatik, Germany
O. Bringmann , FZI Forschungszentrum Informatik, Germany
W. Rosenstiel , Universit?t T?bingen, Germany
In this paper we present an approach for the analysis of systems of parallel communicating processes, with regard to Network-on-Chip applications. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using the results of our method for communication analysis, we present a new method to detect communications that might produce conflicts on shared communication resources. This information can be used to determine static routing in a packet routing network.
A. Siebenborn, O. Bringmann and W. Rosenstiel, "Communication Analysis for Network-on-Chip Design," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 315-320.