Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.36
Marc Franzmeier , University of Paderborn, Germany
Christopher Pohl , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
Ulrich R?ckert , University of Paderborn, Germany
In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times. Our system consists of Processing Elements (PEs) working completely in parallel on the task of SOM simulation. We will show the scalability of the system concerning precision and number of PEs, as well as the flexibility of the system regarding size and shape of the simulated maps. The possibility of emulating virtual maps (one PE emulates more than one neuron) enables the computation of maps with more neurons than PEs. Benchmarking results of our FPGA (Field Programmable Gate Array) based implementation of the system show the high performance of our accelerator.
M. Porrmann, M. Franzmeier, U. R?ckert and C. Pohl, "Hardware Accelerated Data Analysis," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 309-314.