Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.34
Silvio Misera , Brandenburg University of Technology Cottbus
Heinrich Theodor Vierhaus , Brandenburg University of Technology Cottbus
Systems on a chip (SoCs) that consist of one or several processor devices, other complex functional blocks, embedded memories plus multiple interconnects are a big challenge to design and test technology. The simulation of such complex systems under fault conditions is an open problem, since RTL simulators typically do not provide simple means of fault injection and high speed in combination. On the other hand, advance fault simulation tools are be required to validate circuit architectures that provide online test and error correction.<div></div> The work presented here describes the first version of a hierarchical and parallel fault simulation tool that was developed to validate self-test and error correction circuits on SoCs.
H. T. Vierhaus and S. Misera, "FIT - A Parallel Hierarchical Fault Simulation Environment," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 289-294.