Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.61
Dietmar Fey , Friedrich-Schiller-University Jena, Germany
Lutz Hoppe , Friedrich-Schiller-University Jena, Germany
Andreas Loos , Friedrich-Schiller-University Jena, Germany
We present results of an investigation concerning the appropriateness of different parallel SIMD architectures based on reconfigurable approaches for an integration in an one-chip high speed smart CMOS camera. The processing elements (PEs) of the architecture combine parallel analogue optical signal detection and parallel digital signal processing to meet real-time requirements. However, the parallel architecture puts some constraints on the PE architecture. To achieve reasonable pixel resolutions and fill factors the PE area has to be as low as possible. Additionally a single PE must also offer sufficient functional flexibility. We show by a logic synthesis that reconfigurable architectures based on morphological operations are the best solution to fulfill these constraints. Furthermore we present simulation results of a first test chip which we designed as an OPTO-ASIC with a simple SIMD chip architecture.
L. Hoppe, D. Fey and A. Loos, "Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 251-255.