Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.35
H. Seidel , TU-Dresden, Germany
G. Cichon , TU-Dresden, Germany
P. Robelly , TU-Dresden, Germany
M. Bronzel , TU-Dresden, Germany
G. Fettweis , TU-Dresden, Germany
The demand for increasing design complexity has to face decreasing design time and design cost issues. Traditional full custom design flows are not reasonable to cope with this challenges. We have developed a design exploration platform which provides access to main chip design parameters beginning from early design stages. With this platform, architecture and hardware/software partitioning failures are correctable with low change cost in a short time. Our designs are based on Synchronous Transfer Architecture SIMD DSP Cores with a tailored instruction set. Automatic Core Generation Tools speed up the design and verification process. In this paper we present our design exploration platform and a use case study for a DVB-T/H like OFDM-Receiver and Transmitter build with our design methodology.
G. Cichon, M. Bronzel, P. Robelly, H. Seidel and G. Fettweis, "Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 221-225.