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Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Dresden, Germany
Sept. 7, 2004 to Sept. 10, 2004
ISBN: 0-7695-2080-4
pp: 209-214
Michael Thies , University of Paderborn, Germany
Ulrich R?ckert , University of Paderborn, Germany
Adrian Slowik , University of Paderborn, Germany
Dinh Khoi Le , University of Paderborn, Germany
Mario Porrmann , University of Paderborn, Germany
Matthias Gr?newald , University of Paderborn, Germany
J?rg-Christian Niemann , University of Paderborn, Germany
Uwe Kastens , University of Paderborn, Germany
This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processor?s instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly.
Michael Thies, Ulrich R?ckert, Adrian Slowik, Dinh Khoi Le, Mario Porrmann, Matthias Gr?newald, J?rg-Christian Niemann, Uwe Kastens, "Network Application Driven Instruction Set Extensions for Embedded Processing Clusters", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 209-214, 2004, doi:10.1109/PCEE.2004.45
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