Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.24
J. Schneider , FhG-IIS, Germany
V. Kotzsch , FhG-IIS, Germany
St. R? , FhG-IIS, Germany
With this demonstrator we present a new reuse based design methodology for the development of FEC (Forward Error Correction) applications for reconfigurable SoC (System-on-Chip) architectures. This approach enables the reuse of well tested and optimized RS- (Reed-Solomon) codec modules consisting of both HW and SW. Specific RS codec modules can be generated by generator tools. In order to automate the reuse process for dynamically reconfigurable SoCs, the generator tool supports the generation of design modules, interfaces and design flows. We examined our design methodology and RS codec modules within the SFB-358 demonstrator.
J. Schneider, S. R? and V. Kotzsch, "Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 177-180.