Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.1
T. Oppold , University of Tuebingen, Germany
T. Schweizer , University of Tuebingen, Germany
T. Kuhn , University of Tuebingen, Germany
W. Rosenstiel , University of Tuebingen, Germany
There is a growing number of reconfigurable architectures that combine the advantages of a hardwired implementation (performance, power consumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically reconfigured at run-time within one clock cycle. But the benefits of these architectures can only be utilized if applications can be mapped efficiently. In this paper we describe a design environment that takes into account the three aspects architecture, compiler, and applications, and we present the basic techniques that we use to realize the compiler.
T. Kuhn, T. Oppold, W. Rosenstiel and T. Schweizer, "A Design Environment for Processor-Like Reconfigurable Hardware," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 171-176.