Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture
Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.60
Lev Kirischian , Ryerson University Toronto, Canada
Irina Terterian , Ryerson University Toronto, Canada
Pil Woo Chun , Ryerson University Toronto, Canada
Vadim Geurkov , Ryerson University Toronto, Canada
In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx "Virtex" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro-architectures when hardware fault occurs. This Paper presents a description of system level architecture of run-time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.
P. W. Chun, V. Geurkov, I. Terterian and L. Kirischian, "Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 165-170.