Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Sept. 7, 2004 to Sept. 10, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.4
W. Bielecki , Technical University of Szczecin, Poland
R. Kocisz , Technical University of Szczecin, Poland
A technique, permitting us to linearize constraints formed to find affine schedules for arbitrary nested loops, is presented. The main advantage of this technique is that it does not require finding the polytope vertices and results in the fewer number of inequalities and equalities than that yielded with the vertex technique. Affine schedules found are valid for the arbitrary positive lower and upper loop bounds. Experiments with the Livermore loops are discussed. The restriction of the technique and tasks for future research are discussed.
W. Bielecki and R. Kocisz, "A Modified Vertex Method for Parallelization of Arbitrary Nested Loops," Parallel Computing in Electrical Engineering, 2004. International Conference on(PARELEC), Dresden, Germany, 2004, pp. 91-96.