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Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Dresden, Germany
Sept. 7, 2004 to Sept. 10, 2004
ISBN: 0-7695-2080-4
pp: 85-90
Sebastian Siegel , Dresden University of Technology, Germany
Renate Merker , Dresden University of Technology, Germany
ABSTRACT
This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.
INDEX TERMS
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CITATION
Sebastian Siegel, Renate Merker, "Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 85-90, 2004, doi:10.1109/PCEE.2004.10
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