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Parallel Computing in Electrical Engineering, 2004. International Conference on (2004)
Dresden, Germany
Sept. 7, 2004 to Sept. 10, 2004
ISBN: 0-7695-2080-4
pp: 71-76
Tomasz Madajczak , Technical University of Gdansk, Poland
ABSTRACT
This document presents a theoretical analysis of state-of-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficient method of hardware threading in certain scenarios.<div></div> The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.
INDEX TERMS
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CITATION
Tomasz Madajczak, "An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures", Parallel Computing in Electrical Engineering, 2004. International Conference on, vol. 00, no. , pp. 71-76, 2004, doi:10.1109/PCEE.2004.13
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